Typical electronic packages of the type described above include a dielectric substrate as a critical element thereof, this substrate, e.g., of ceramic or a suitable polymer material such as fiberglass-reinforced epoxy resin (FR4), having the various desired conductive layers located thereon and/or therein.
One representative example of such a multileveled electronic package is referred to in the industry as a multileveled ceramic polyimide (MCP) package which utilizes a ceramic substrate having thereon at least two conductive layers, e.g. , copper, separated by an interim layer of dielectric (in the case of MCP, typically polyimide). Such a package structure may further include conductive pins or the like projecting from an external surface thereof (opposite the surface of the substrate having the aforementioned layers thereon) for being inserted with associated conductive receiving means, e.g., metallic sockets, located with a second substrate such as a printed circuit board (PCB) or the like. Such a package also typically includes one or more (usually several) semiconductor devices (chips) located on the upper surfaces of the substrate and electrically coupled to the individual conductive layers as deemed necessary. It is known in the art to provide such connections using solder, with one very well known and widely accepted process for doing so developed by the assignee of the instant invention. This process is referred to in the industry as controlled collapse chip connection (C-4), said process described in various publications (including patents). Further description is thus not believed necessary.
Examples of various electronic packages of the type referred to herein are also described in the following identified U.S. Letters Patents:
U.S. Pat. No. 4,430,365--Schaible et al.
U.S. Pat. No. 4,446,477--Currie et al.
U.S. Pat. No. 4,805,683--Magdo et al.
U.S. Pat. No. 4,835,593--Arnold et al.
Further attention is also directed to the following International Business Machines (IBM) Corporation Technical Disclosure Bulletins (TDBs) for descriptions of various ceramic substrates having circuitry thereon:
IBM TDB Vol. 22, No, 10, March, 1980
IBM TDB Vol. 32, No. 10A, March, 1990
In one known process for manufacturing an MCP package which will include at least one chip electrically coupled to the circuitry thereof, the process begins with the deposition of a first layer of metal on the ceramic's top surface. This layer is initially comprised of chromium-copper-chromium (Cr--Cu--Cr) and is sputter deposited using known sputtering techniques. A layer of photoresist is then used to cover the Cr--Cu--Cr layer, this layer then subjected to a series of photolithography steps (soft bake, expose, develop and bake) to form a desired pattern of such resist on the Cr--Cu--Cr. Areas of unprotected metal in the underlying Cr--Cu--Cr layer are then removed using a known etching operation. The remaining protective pattern of resist is then removed (stripped) to expose the desired circuit pattern remaining on the ceramic's top surface. This pattern, understandably, includes at least one and preferably several contact locations, each of which is adapted for being electrically coupled to a respective contact site on the chip (s) . In the next step in the operation, a layer of dielectric, e.g. , polyimide, is then deposited over the entirety of the remaining circuit pattern, including the contact locations, such deposition referred to in the industry as blanket coating (meaning to cover the entire circuitry). Another series of photolithography steps are performed on the polyimide to define a pattern of openings (which are referred to as "vias"), selected portions (those which have been developed) of the dielectric polyimide then being removed to thereby expose parts of the circuitry thereunder. Understandably, the aforementioned contact locations are so exposed. At this point, the polyimide is baked and raised to a high cure state. In an alternative operation, laser ablation may be used instead of the chemical processing which forms part of the described photolithography steps to effect the desired selective removal of polyimide. The top layer of chromium of the Cr--Cu--Cr layer is then removed using a known etching operation, such that the remaining exposed parts of the layer (the contact locations) are comprised of an upper portion of copper and a minute layer of chromium (which promotes adhesion of the copper-chromium to the ceramic).
In the next step of this manufacturing operation, a second layer of metal is deposited over the polyimide and the exposed conductive contact locations. A procedure known as a batch evaporation process is used, the result being that a layer comprised of chromium-copper-chromium is again formed. The aforementioned batch evaporation process is used at this stage rather than the described sputtering step because such a process has a prolonged heat cycle that serves to drive off solvents and water vapor which might remain and possibly interfere with the resulting interconnections between conductive layers. The previously described photolithography and wet processing steps are then repeated to define a second desired pattern for the second conductive layer. Final photolithography patterning followed by top chromium etch is then performed to selectively remove the chromium originally found in the top conductive layer. As in the case of the underlying first conductive layer, this second conductive layer will include at least one and preferably several contact locations for providing chip coupling.
The result of the above process is the formation of at least two conductive layers on the upper surface of the dielectric ceramic, each of these layers with at least one contact location thereon which is adapted for being electrically coupled, e.g., using solder as mentioned above, to respective contact sites on a chip which is then to be located over the exposed contact locations and coupled thereto. As further understood, these conductive layers are also separated by the dielectric layer of polyimide, which serves to electrically insulate the two as is necessary for successful operation of the package.
At least two disadvantages are associated with the above-described manufacturing process. One is that this process requires the performance of several diverse steps, requiring relatively large periods of time and the use of elaborate and expensive equipment. A second is that the process requires the formation of metal-to-metal interconnections at selected locations (those contact locations of the first layer with metal from the second conductive layer). Such interconnections are susceptible to variations in electrical resistance, which is of course highly undesirable in the manufacture of such precision-demanding products as multileveled electronic packages. To assure reliability between such interconnections to the levels demanded in this industry, special control measure and test operations are essential. This also adds to the overall costs of the final packages.
As will be described herein, the present invention describes a multilevel electronic package wherein at least two conductive layers are used, each with individual contact locations for being electrically coupled to respective contact sites on a semiconductor chip. Significantly, the contact locations of one layer are located at a greater distance (elevation) above the dielectric substrate's upper surface while still being directly electrically coupled to the respective chip contact sites. As will be further described herein, the process for manufacturing such a product is capable of being performed with fewer steps and in less time than the aforementioned process for the MCP product described above. Equally significant, this process results in a product wherein metal-to-metal interconnections between separate metal conductor levels are unnecessary, thereby overcoming the above-mentioned disadvantages associated therewith. Although the present invention is particularly adapted for the manufacture of MCP products, this is not meant to limit the invention in that the process as defined herein may be readily adapted for utilization with other types of substrate packages, including those which use known FR4 and other dielectric materials for the base substrate member.
It is believed that such an electronic package and process for manufacturing same would represent a significant advancement in the art.